Package Substrate In-Plane (Areal) Coefficient of Thermal Expansion Testing: Methods, Standards, and

Package substrate in-plane coefficient of thermal expansion (CTE) testing quantifies the dimensional stability of organic and flexible substrate materials in the X–Y plane, a parameter that directly governs solder joint reliability, die-substrate stress, and package warpage. This article explains the testing principles, applicable standards such as IPC-TM-650, ASTM E831, ISO 11359-2, and JIS C 6481, typical sample requirements, data interpretation, and industrial applications of areal expansion coefficient measurement for advanced IC packaging.

Technical Overview

Package substrates provide the electrical and mechanical interconnection between the silicon die and the printed circuit board in flip-chip, ball grid array (BGA), chip-scale package (CSP), and 2.5D/3D architectures. Because the silicon die expands at approximately 2.6 ppm/°C while organic substrate cores typically expand at 6 to 20 ppm/°C in the X–Y plane, every thermal excursion during reflow, thermal cycling, and field operation generates shear strain in the solder joints and tensile stress in low-k dielectric layers. The in-plane (areal) coefficient of thermal expansion is therefore one of the most critical material parameters in package design and reliability engineering.

The linear in-plane CTE (αL) is defined as the fractional change in length per unit temperature change, expressed in ppm/°C, while the areal expansion coefficient (αA) describes the fractional change in planar area with temperature. For materials with small, isotropic in-plane expansion, the areal coefficient is approximately twice the linear coefficient (αA ≈ 2αL). In practice, most specifications and incoming-inspection documents for package substrate materials report directional X and Y linear CTE values over defined temperature windows such as 25–100 °C, 25–150 °C, or pre- and post-Tg segments (α1 and α2).

Testing is typically performed by accredited third-party laboratories or in-house materials laboratories according to recognized industry standards, including IPC-TM-650 method 2.4.24.1 (X–Y axis CTE by thermomechanical analysis), ASTM E831 (linear thermal expansion by TMA), ASTM E228 (dilatometry), ASTM D696, ISO 11359-2, JIS C 6481, and GB/T 1036, with material-level acceptance limits defined in specification documents such as IPC-4101 and IPC-4103 slash sheets. Related system-level behavior is often cross-referenced with JEDEC JESD22-B112 warpage-at-temperature measurement and IPC-9701 thermal cycling performance.

Testing Samples

Core Materials and Copper-Clad Laminates

Rigid substrate cores such as bismaleimide-triazine (BT), high-Tg epoxy-glass, modified-epoxy, and low-CTE glass or carbon-fiber reinforced laminates are tested as representative plaques or production panels. Specimens are usually cut as small squares or strips, for example 6 mm × 6 mm to 10 mm × 10 mm for TMA or longer strips for dilatometry, with thickness taken as supplied.

Build-Up Dielectric Films

Photo-imageable and thermally cured build-up dielectric films used in sequential build-up (SBU) layers are laminated onto carrier frames, cured under production-representative profiles, and then cut into specimens. Because these resin-rich layers generally show higher expansion than glass-reinforced cores (commonly 20 to 60 ppm/°C below Tg), their CTE strongly influences bump pad cracking and microvia reliability.

Finished Package Substrates

Completed BGA, flip-chip, and CSP substrates can be tested after final fabrication, with copper patterns either etched away to isolate the dielectric response or retained to evaluate the composite behavior of the finished board. Both conditions are acceptable provided the reporting states which configuration was measured.

Flexible and Specialty Substrates

Polyimide-based flexible substrates, adhesiveless copper-clad films, and glass or silicon interposer candidates are also characterized for in-plane CTE, since these materials are increasingly used where closer CTE matching to silicon is required.

Common specimen preparation and conditioning requirements include:

• Conditioning at 23 ± 2 °C and 50 ± 5% relative humidity, or dry-baking at approximately 105 °C for 1 to 2 hours to remove absorbed moisture that can distort the expansion curve.
• Cutting clean, parallel edges free of cracks and delamination, since edge defects introduce artificial length changes.
• Recording fiber direction so that warp (X) and fill (Y) anisotropy can be reported separately.
• Documenting cure state and thermal history, because residual stress relaxation on first heating can bias the measured expansion.

Testing Items

Typical measured and reported quantities for in-plane expansion testing of package substrate materials include:

• Linear in-plane CTE in the X and Y directions, in ppm/°C, over specified ranges such as 25–100 °C, 25–150 °C, or 30–125 °C.
• Areal (planar) expansion coefficient, derived as approximately twice the average in-plane linear CTE for small expansions.
• α1 (below Tg) and α2 (above Tg) expansion segments, together with the glass transition temperature identified from the slope change of the dimension-versus-temperature curve.
• X–Y anisotropy ratio arising from glass fabric weave geometry, which drives directional warpage in asymmetric designs.
• Full dimension-change (ΔL/L0) versus temperature curves and the numerical derivative used for CTE extraction.
• Optional conditioning studies: CTE after moisture absorption, after reflow simulation to 260 °C, or after multiple thermal cycles.

Testing Methods

Thermomechanical Analysis (TMA)

TMA is the dominant method for package substrate in-plane CTE and follows IPC-TM-650 2.4.24.1, ASTM E831, and ISO 11359-2. The specimen is placed on a flat quartz platform with a low-mass expansion probe applying a small static force, typically 0.05 to 0.3 N. The furnace is heated at a controlled rate, commonly 5 °C/min, under nitrogen purge from room temperature to 260 °C or beyond Tg as required. In-plane (X–Y) measurement uses lateral specimen geometry on the platform, whereas the related Z-axis method (IPC-TM-650 2.4.24) measures through-thickness expansion. Where thermal history effects are significant, a first heating scan relieves residual stress and the second scan is reported.

Quartz Dilatometry

For longer specimens and lower-temperature windows, push-rod dilatometry per ASTM E228 or ASTM D696 offers excellent precision. A vitreous silica dilatometer measures the expansion of a strip-shaped specimen against a calibrated reference, making the method well suited to verifying TMA results or evaluating large production panels where localized material variation must be averaged out.

Optical Full-Field and Strain-Based Methods

Digital image correlation (DIC), laser displacement sensing, moiré interferometry, and vision-based metrology provide non-contact, full-field in-plane expansion and can be combined with reflow-profile heating to capture transient warpage-coupled behavior consistent with JEDEC JESD22-B112 concepts. These techniques are particularly valuable for finished substrates with complex copper distribution, where the effective composite CTE differs from the neat material value.

Data Reduction and Areal Conversion

The linear CTE between two temperatures is calculated as α = (1/L0) × (ΔL/ΔT), where L0 is the initial dimension at the reference temperature. The areal coefficient is computed from planar area change, αA = (1/A0) × (ΔA/ΔT), which for small isotropic in-plane expansion reduces to αA ≈ 2αL. Reports should state the reference temperature, averaging window, heating rate, atmosphere, scan number, and measurement uncertainty, which is typically within ±0.5 to 1 ppm/°C for in-plane TMA when calibrated against reference expansion standards.

Applications

In-plane CTE test data from package substrate materials are used throughout the electronics supply chain:

• Material qualification and incoming inspection of cores, prepregs, and build-up films against supplier specifications and IPC-4101/IPC-4103 slash-sheet limits.
• Package design and warpage simulation, where measured X and Y CTE values feed finite-element models that predict reflow warpage and non-wet open joints.
• Solder joint reliability assessment, supporting strain-range inputs for fatigue life models under thermal cycling per IPC-9701 and automotive grade requirements.
• Advanced packaging development, including flip-chip BGA, chip-scale packaging, fan-out redistribution, embedded die, and 2.5D/3D interposer stacks requiring close CTE matching to silicon.
• Failure analysis, where anomalous α1/α2 values or unexpected Tg shifts reveal under-cure, moisture uptake, resin degradation, or lot-to-lot material drift.
• Automotive, aerospace, and 5G/RF applications in which extended temperature ranges and low-loss, low-expansion materials impose tighter CTE control.

FAQ

Why is in-plane CTE so important for package substrates?

The in-plane CTE mismatch between the silicon die, the substrate, and the system board drives solder joint shear strain during thermal excursions. Excessive in-plane expansion accelerates joint fatigue, induces package warpage at reflow temperature, and can crack low-k dielectric layers and fragile bump structures, so designers specify tight CTE windows to guarantee assembly yield and long-term reliability.

What are typical in-plane CTE values for package substrate materials?

BT and high-Tg epoxy-glass cores generally exhibit approximately 10 to 17 ppm/°C below Tg, low-CTE reinforced cores can reach 3 to 10 ppm/°C, and resin-rich build-up films commonly fall between 20 and 60 ppm/°C. For comparison, silicon is about 2.6 ppm/°C and copper is about 17 ppm/°C, which explains why heavy copper planes raise the effective in-plane expansion of a finished substrate.

What is the difference between linear and areal expansion coefficients?

The linear coefficient describes fractional length change in one direction, while the areal coefficient describes fractional change of the planar area. Because area scales as length squared, the areal coefficient of an in-plane isotropic material equals approximately twice its linear coefficient, and both conventions are accepted provided the report defines which one is used.

How do in-plane and Z-axis CTE differ for the same substrate?

Glass-fiber reinforcement constrains expansion in the X–Y plane, while the resin-rich thickness direction expands far more freely. As a result, Z-axis CTE is commonly several times higher than in-plane CTE and increases sharply above Tg, affecting plated hole and microvia reliability, whereas in-plane CTE dominates die stress and warpage behavior.

Which temperature range should be specified for reporting?

The reporting window must reflect the intended use condition. Common choices include 25–100 °C or 30–125 °C for operating conditions, 25–150 °C to include power cycling, and heating to 260 °C to simulate lead-free reflow, with α1 and α2 reported separately around the glass transition so that both the glassy and rubbery expansion regimes are documented.

Can finished substrates with copper patterns be tested directly?

Yes. Testing as-fabricated substrates yields the effective composite in-plane CTE that the die actually experiences, while etching the copper away isolates the dielectric contribution. Both approaches are valid; the key is consistency between the test configuration, the specification limit, and the simulation input for which the data will be used.

What factors most affect measurement accuracy?

Specimen flatness, moisture conditioning, residual stress relaxation on first heating, probe force calibration, furnace thermal gradients, and correct identification of the averaging window are the main influences on accuracy. Using calibrated reference materials, a nitrogen atmosphere, and second-scan reporting per the applicable IPC, ASTM, ISO, or JIS procedure minimizes scatter and ensures inter-laboratory comparability.